August 2016 Newsletter: Volume 3, Issue 3

A Message from the Director, Jian-Ping Wang

C-SPIN hosted two important events in May. First, we had another successful mid-term review. I was glad to see many exciting results and good dynamics among the PIs. In fact, many of the good results couldn’t have happened without the teamwork instigated by C-SPIN. All the PI presentations were sent to our sponsors for further discussion. Second, we had a great workshop on topological spintronic devices that attracted 23 world-leading researchers (including Nobel Laurette Prof. Albert Fert) as invited speakers and over 75 participants from both industry and academia. Mike Lotti, our communications assistant, held interesting interviews with speakers that led to three videos: one on C-SPIN, one on topological insulators, and one that captures the interview with Albert Fert.

C-SPIN hosted another important event in June. Prof. Sachin Sapatnekar and Prof. Kaushik Roy organized a timely spintronic devices workshop at the DAC conference in Austin with speakers from IBM, Intel, and many universities.

C-SPIN PIs and students have continued to generate exciting results. Our students presented their results at DRC and DAC conferences, and Prof. Mingzhong Wu published his new demonstration of spin Hall induced switching in perpendicular magnetic oxide (BaM) in a recent issue of Nature Communication.

The beautiful summer is approaching its end, which means that C-SPIN will have its 4th annual review soon - September 20-22, to be precise. Besides the full review on Sept 21-22, we will have a half day focus session workshop on spin memory and computing Sept 20. Registration for both events is now open.

Thanks to Mike and Marie again for preparing this issue of newsletter.

Q&A with Prof. X. Sharon Hu, Univ. of Notre Dame

From C-SPIN Director Jian-Ping Wang: In our last newsletter, STARnet Program Director Todd Younkin told us that now “is a time to focus, be highly productive, push forward the good ideas, and be cognizant of leaving your legacy.” (And if you haven’t yet read that interview, you really should.) With Younkin’s words in mind, we brought Prof. X. Sharon Hu from Notre Dame into the Center. Her impressive work at all levels of computing technology shows that she likes to “get things done” and that she’s comfortable with large-scale collaborations that include industry. Below is a Q&A she conducted with our communications specialist Mike Lotti.

X. Sharon Hu X. Sharon Hu, Univ. of Notre Dame

Q: How did you get involved in C-SPIN?
Jian-Ping Wang was familiar with my work as a member of LEAST, a STARnet center based at the University of Notre Dame. Within LEAST, my work has been centered around investing novel ways to exploit steep slope transistors at the circuit/architecture​ levels and benchmarking these beyond-CMOS devices. My other research efforts also involve developing circuits and architectures based on spintronic devices – in particular, nanomagnet logic and STT-RAM. In one way or another, all of that is applicable to C-SPIN’s current needs. I look forward to applying my experience​s to help understand how the novel devices being investigated in C-SPIN can be exploited at the application level.

Q: What are your primary tasks in C-SPIN?
A: Since I began in May, benchmarking spintronic devices at the architecture and application levels has been my primary focus. A relatively straightforward way of benchmarking C-SPIN is to directly compare a spintronic device to its CMOS counterpart for drop-in replacement. However, device performance may not be a good indicator of system performance, so benchmarking has to incorporate everything between devices and the entire system. In addition, improvements are happening all the time, so I’m trying to develop a way to update and expand the Center’s benchmarking on a regular basis.

As a member of the Theme 5 team, I am also exploring novel applications for spintronic devices. In other words, I’m examining  new applications and architecture approaches that will drive the use and development of devices. I have been having some regular meetings with Sachin Sapatnekar, Chris Kim, and Jian-Ping, and I expect to be working with the other Theme 5 PIs soon. The Mid-Term Review in May gave me an appreciation of C-SPIN’s accomplishments in terms of exciting new materials, devices, and possibilities,  so I expect to work in the “devices to architectures mapping” direction too.

Q: What other work are you doing in your lab?
A:  My lab works closely with beyond-CMOS transistor researchers to design and benchmark circuits, architectures, and applications​ that are made of these transistors. We are also studying resource management in cyber-physical systems where quality of service, energy, and reliability are of particular concern – a direct outgrowth of my years as a researcher for GM. Cyber-physical systems are all around us and their complexities are increasing faster than ever. However, handling such complexities in a systematic way with a sound theoretical basis is a huge challenge. A good, everyday example is a car. Every car these days has dozens or even hundreds of microprocessors for sensing, processing, communicating, and even decision-making. Most of these have been added to a basic car design in an ad hoc fashion over the years. We’re trying to be more systematic, starting from the device/circuit level (what kind of chips work best in these environments?) and going all the way to the system level (can we integrate systems and reduce maintenance? Can we move processing closer to sensing?). As C-SPIN PIs know, this means working hard to get people with different specialties to work together, and it also means a lot of interfacing with industry.

Although this research isn’t directly connected to C-SPIN, I’m starting to see connections. Since learning more about spintronics, I’ve started to suspect that spin-based materials and devices could significantly improve some specific aspects of cyber-physical systems. I anticipate some interesting conversations with C-SPIN colleagues over the next year.

Q: You’ve worked on computer design at all levels for over two decades. What do you think the computers of the future will look like?
A: In plain language, they will be heterogeneous systems. There will still be a central processor that will most likely be CMOS-based, but a lot of special tasks will be “outsourced” to special-purpose processors, probably combinations of CMOS and non-CMOS processors with novel architectures. It’s becoming clearer that functions like image/voice/video processing, big data analytics, and optimization tasks can be done more efficiently with non-traditional architectures and/or non-CMOS devices. Storage/memory is another area that will see some exciting advances based on new architectures and devices. I strongly believe that C-SPIN is uniquely positioned to make big contributions to these areas. 

A Successful Topological Spintronic Devices Workshop

In May, C-SPIN sponsored the first-ever workshop dedicated to the science and possibilities of topological spintronic devices. By all measures, the event was a success. Over 95 people showed up to hear 2007 Nobel laureate kick off the Workshop, and over 75 attended some or all of the 23 other presentations (many of which are still available on the workshop webpage). The Workshop hosted participants from academia and industry, including eight C-SPIN PIs and two C-SPIN industry liaisons.

While we had so many notable scientists in one place, we made a short video about the promise of topological insulators. We also posted our entire interview with Albert Fert.

Registration for the 2016 C-SPIN Annual Review

The C-SPIN 2016 Annual Review will be held at the University of Minnesota, Minneapolis September 20-22, 2016. The review will be preceded by a half-day focus session workshop on September 20th (starting at 12pm CT). This workshop will be comprised of two focus sessions dedicated to topics of current and future interest to C-SPIN.

  • Focus Session 1: Spin Computing: non-Boolean and non-Von Neumann computing and their realization. Confirmed presenters: Sharon Hu (Notre Dame), Kaushik Roy (Purdue), Trung Tan (DARPA)
  • Focus Session 2: Spin Memory: what comes after STT-RAM? Confirmed presenters: Maxim Tsoi (U Texas at Austin), Chia-Ling Chien (Johns Hopkins), Janusz Nowak (IBM), Witold Kula (Micron)

The annual review will begin on the morning of September 21st and will wrap-up late in the afternoon on the 22nd. There will be a reception and dinner for all review attendees the evening of the 21st. Please see the agenda page for more details about the review schedule.

Please visit the C-SPIN website to REGISTER. Registration closes August 22nd.

The deadline for making hotel reservations is also August 22nd. Please visit the Annual Review homepage for more details about the review. Questions regarding the review can be directed to Marie L. Rahne at: cspin (AT)

Student and Post-Doc Profiles

Seyed Armin Razavi Seyed Armin Razavi

Seyed Armin Razavi

Ph.D. candidate, UCLA

I am working on antiferromagnetic spin-orbit torque memory devices for Theme 4 in Prof. Kang Wang’s lab at UCLA. In theory, these devices offer good endurance, zero standby power dissipation, low dynamic power dissipation, and high bit density. But switching the perpendicular magnetization requires an extra in-plane magnetic field to allow for deterministic switching, which is not a practical solution in industrial applications. So we are trying to replace the need for the external field with an exchange bias field at the interface between a ferromagnetic and an anti-ferromagnetic material. So far, we have achieved field-free switching in a prototype version, and we are trying to improve this prototype and embed it in more practical structures. These devices can be building blocks for low-power and scalable memories in spin-based computational systems.

I am also working on ultrafast all-optical switching of magnetization, which is a rather newly discovered process in which magnetization reversal happens in a very fast non-equilibrium mechanism. Moreover, it's only done with a circularly polarized laser pulse – i.e. it does not require an external magnetic field. Since this is only my second year as a graduate student, I don’t have any publications yet. But my first paper – which is on my C-SPIN work – has just been submitted.

My interest in physics and mathematics led me to where I am today. I have always thought these are the most important and fundamental subjects for exploring the world. But I am also intensely interested in applying knowledge, so I chose electrical engineering as a field of study. C-SPIN work suits me well because it’s engineering that requires a lot of physics.

My current career goal is to contribute to the development of more powerful computational systems. Despite all the advances in computer technologies over the past 60 years, I think we are only at the beginning of what computers can do. We still cannot simulate complicated systems, and we still cannot solve very complicated mathematical problems. The growth in computing power has led to progress, and more growth will do the same. By opening the door to larger capacity and more efficient computing, we are really offering a benefit to all the fields of science. My hope, then, is to continue to work as a researcher after my PhD studies.

Student Name Robert Perricone

Robert Perricone

Ph.D. candidate, University of Notre Dame

My current work for C-SPIN involves the design and evaluation of non-volatile processors comprised of C-SPIN devices. This work falls under Themes 4 and 5. I consider whether the characteristics of the spin-based device and the target applications can be exploited to produce an architecture that is competitive with its CMOS-based counterpart. I also contribute to the evaluation (i.e., benchmarking) of C-SPIN device technologies at the architectural/application level.

I have also worked within STARnet’s LEAST center for the last three years. My initial projects involved designing and evaluating circuits and architectures based on nanomagnetic logic (NML) devices. More recently, my work has focused on developing a methodology for benchmarking transistor-like devices at the architectural/application level. I have six publications based on my NML and architectural-level benchmarking work.

From a young age, I was fascinated by computers (maybe even a bit obsessed with them). Through elementary and high school, I noticed how computers were becoming more ubiquitous, so I decided pursue electrical and computer engineering in college. While in college, I learned about Moore's Law and its relation to CMOS transistors. I simply asked myself, "What is beyond Moore's Law? What happens when we hit the limits of CMOS scaling?" From there, I began my journey down the beyond-CMOS rabbit hole by applying to graduate computer engineering programs with the desire to study new devices and architectures and, hopefully, contribute to the beyond-CMOS era. I love having the opportunity to work with cutting-edge technologies that have the potential to impact the future of microprocessors.

I definitely want to continue working as a researcher either within academia or industry. I hope to continue working with emerging technologies and influence future microprocessor design and implementation. At some point, I would also like to teach and work with students to inspire the next generation of computer scientists and engineers.